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A team of researchers led by Stanford'south Mohamed M. Sabry Aly, Subhasish Mitra, and H.-S. Philip Wong desire to put a "skyscraper" of estimator chips in your next PC. The idea is to stack application processors, memory modules, and other components i on top of the other in "a revolutionary new loftier-ascent architecture for computing," according to the Stanford News Service.

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Such an "electronic super-device" using the team's Nano-Engineered Computing Systems Technology, or N3XT, could power a computer which combines "higher speed with lower free energy use [to] outperform conventional approaches past a factor of a g," Wong told Stanford'south news journal.

Stacking chips has long been seen as a viable path towards building a more efficient, powerful computing architecture than the current template, which lays out and connects components on a flat lath, like "single-story structures in a suburb," as the researchers put information technology. Merely edifice a "skyscraper" of fries has thus far proven difficult using silicon-based integrated circuits (ICs), which are tough to connect reliably in a stacked structure.

Sabry Aly, Mitra, Wong, and their colleagues believe they've figured out a way around such issues using "new nano-materials" to construct stacked computer chips in place of traditional silicon ICs. Dubbed Nano-Engineered Computing Systems Engineering science, or N3XT, the procedure involves building carbon nanotube transistors (CNTs) in a stacked arrangement. The effect is that instead of the relatively limited number of wires connected stacked silicon chips, a N3XT device could apply "millions of electronic elevators that tin can move more data over shorter distances that traditional wire, using less energy," per the researchers.

Instead of adding traditional wires to connect stacked chips in a N3XT organization, communication betwixt components is built in during the bodily process of fabrication. Since CNTs can exist created at much lower temperatures than silicon-based transistors, it'due south possible to build components on tiptop of each other, like a processor on a memory module, while maintaining the integrity of those tiny "electronic elevators," the researchers noted. Silicon ICs, on the other manus, have to exist fabricated separately from each other and so stacked in "3D" arrangements later, which precludes integrating those interconnects from the go-go.

The squad is also incorporating cooling in its N3XT devices, just as traditional two-dimensional computing architectures must have their thermals kept in cheque to prevent overheating. Stanford mechanical engineers Kenneth Goodson and Mehdi Asheghi are leading the effort to "incorporate thermal cooling layers" in the stacked fries, according to Stanford News Service.

The team has published its findings in a recent special upshot of IEEE Computer.

One major roadblock to the adoption of N3XT or chip-stacking technologies like information technology? The global semiconductor industry is massively invested in silicon-based process technology, the researchers noted.

"Shifting electronics from a low-rising to a high-rise architecture volition demand huge investments from industry," they were quoted as proverb.

Notwithstanding, the incentive to do then is compelling, said N3XT commodity co-author Chris Re, a Stanford estimator scientist and MacArthur Foundation "genius grant" winner.

"There are huge volumes of data that sit inside our reach and are relevant to some of social club's most pressing problems from health care to climate modify, but nosotros lack the computational horsepower to bring this data to low-cal and use it," Re told Stanford News Service. "As we all hope in the N3XT project, we may have to heave horsepower to solve some of these pressing challenges."